1. Field
Embodiments of the present invention relate to a control circuit and switching power supply of a flyback type switching power supply device that converts the voltage of an AC input that turns a switching element on and off into a predetermined direct current voltage and supplies the voltage to a load, and in particular, relate to a control circuit and switching power supply of a switching power supply device that can combat fluctuation due to the voltage value of the AC input in an overcurrent peak current flowing through the switching element.
2. Description of the Related Art
FIG. 5 shows a circuit configuration of a flyback power supply using a PWM controlling integrated circuit (IC).
An AC input 1 is supplied via a transformer 2 and capacitor 3 configuring an input filter to a diode bridge 4, and rectified to a direct current input voltage. A capacitor 5 is provided between the diode bridge 4 and a ground, and has a function of absorbing switching noise. Also, a diode 6 supplies the half-wave rectified AC input 1 via a current limiting resistor 7 to a VH terminal of a control IC 8. Current input into the VH terminal is limited by the current limiting resistor 7.
A thermistor 9 for carrying out heated latch protection of the control IC 8 is connected to an LAT terminal of the control IC 8. Also, the voltage of a sense resistor 12 is input via a noise filter formed of a capacitor 10 and resistor 11 into an IS terminal of the control IC 8. A VCC terminal of the control IC 8 is connected to one end of a capacitor 13, and is connected via a backflow preventing diode 14 to an auxiliary winding 15 of a transformer T. The capacitor 13 holds a power supply voltage supplied to the control IC 8 when a PWM control operation is carried out. Also, the backflow preventing diode 14 acts so as to prevent a backflow of current from the VCC terminal to the auxiliary winding 15.
One end of a primary winding 16 of the transformer T is connected to the capacitor 5, while the other end is connected to the drain terminal of a MOSFET 17. Also, the source terminal of the MOSFET 17 is earthed via the sense resistor 12, and a drain current Ids flowing through the MOSFET 17 is detected by the sense resistor 12. That is, an on-state current of the MOSFET 17 is converted in the sense resistor 12 into a voltage signal of a size proportional to the on-state current, and the voltage signal is supplied via the noise filter to the IS terminal of the control IC 8.
One end of a secondary winding 18 of the transformer T is connected to a diode 19, and also earthed via a capacitor 20. The voltage of the capacitor 20 is sent from the secondary side to the primary side by a photocoupler 21 as information relating to the output voltage supplied to a load 25. That is, the photocoupler 21 is connected in series to a shunt regulator 22, a connection point of resistors 23 and 24 that divide the output voltage is connected to the shunt regulator 22, and the divided output voltage value and an unshown reference voltage are compared by the shunt regulator 22. As a result of this, information on an error in the secondary side output voltage with respect to the reference voltage is converted into a current signal, and load information is sent to the primary side by the current signal driving the photocoupler 21.
In a switching power supply device configured using the PWM controlling control IC 8, the rectified AC input voltage is converted via the transformer T into a predetermined DC voltage by a switching operation of the MOSFET 17 being controlled. In the control IC 8 configured of an IC circuit, load information output to the load 25 on the secondary side of the transformer T is fed back to an FB terminal of the control IC 8 via the shunt regulator 22 and photocoupler 21, as heretofore described, and detected. Also, the voltage of the MOSFET 17 drain current is converted in the sense resistor 12, and the voltage is detected by the IS terminal of the control IC 8. By the FB terminal voltage and IS terminal voltage being compared, and the on-state duration of the MOSFET 17 being variably controlled from an OUT terminal, it is possible to perform the PWM control of the switching power supply device, and thus possible to regulate the power supplied to the secondary side load 25.
FIG. 6 is a block diagram showing an internal circuit configuration of a related PWM controlling control IC.
A start-up circuit (Startup) 31 supplies current from the VH terminal to the VCC terminal when starting up, and on the AC input 1 being applied to the flyback power supply, current flows in the control IC 8 from the VH terminal via the start-up circuit 31 to the VCC terminal. Because of this, the capacitor 13, which is externally connected to the VCC terminal, is charged, and the voltage value thereof rises.
A low voltage malfunction prevention circuit (UVLO) 32 is connected to the VCC terminal and a reference power supply V1. The low voltage malfunction prevention circuit 32 is such that a UVLO signal, which is the output of the low voltage malfunction prevention circuit 32, changes to an L (Low) level on the voltage value of the VCC terminal rising to or above the reference power supply V1, an internal power supply (5VReg.) 33 starts up, and a supply of power to each circuit in the control IC 8 is carried out, while conversely, the UVLO signal is at an H (High) level while the VCC terminal voltage is low, stopping the operation of the control IC 8.
An oscillator (OSC) 34 is connected to the FB terminal, and a frequency modulation function is incorporated therein in order to reduce EMI (electromagnetic interference) noise generated by a switching operation of the MOSFET 17. The oscillator 34 determines the switching frequency of the MOSFET 17 according to the control IC 8, also has a function, separate from the heretofore described frequency modulation function, of lowering the oscillation frequency when there is a light load, and outputs an oscillating signal (a maximum duty cycle signal) Dmax. The oscillating signal Dmax is a signal with a long H level time that changes to an L level for a short time in every cycle, the cycle thereof is the switching cycle of the switching power supply, and the ratio between the cycle and the time of the H level during the cycle provides a maximum time ratio (maximum duty cycle) of the switching power supply. Also, a slope compensation circuit 35 is connected to the IS terminal, and includes a function of preventing sub-harmonic oscillation, of a kind to be described hereafter.
An FB comparator 36 is connected to the FB terminal and a reference power supply V2. When the FB terminal voltage falls below the reference power supply V2, it is determined that the output voltage is excessive, and a clear signal CLR is output from the FB comparator 36 to a one-shot circuit 37 of a subsequent stage, stopping the switching operation. The one-shot circuit 37 is triggered by the rise of the oscillating signal Dmax of the oscillator 34, and generates a set pulse for an RS flip-flop 38 of a subsequent stage. Also, while the H level clear signal CLR is being input, the one-shot circuit 37 does not output a set pulse for the RS flip-flop 38.
The RS flip-flop 38, together with an OR gate 39 and an AND gate 40, forms a PWM signal. That is, a blanking signal, which is a sum (OR) signal of two input output signals—the output signals of the one-shot circuit 37 and RS flip-flop 38—is generated in the OR gate 39. Basically, the blanking signal forms the PWM signal, but furthermore, the maximum duty cycle of the PWM signal is determined in the AND gate 40 based on the oscillating signal Dmax of the oscillator 34.
The UVLO signal output from the low voltage malfunction prevention circuit 32 is supplied via an OR gate 41 to a drive circuit (OUTPUT) 42, and the gate of the MOSFET 17 is on/off controlled by a switch signal Sout output via the OUT terminal from the drive circuit 42. That is, when the VCC terminal voltage is low and the UVLO signal is at an H level, the output of the drive circuit 42 is turned off (a signal causing the MOSFET 17 to be turned off is output). Conversely, when the VCC terminal voltage is high and the UVLO signal is at an L level, the drive circuit 42 on/off controls the gate of the MOSFET 17 in accordance with the output signal of the AND gate 40.
A level shift (Level Shift) circuit 43 has a function of shifting the level of the FB terminal voltage to a voltage range that can be input into an IS comparator 44, and the output signal of the level shift (Level Shift) circuit 43 is supplied to the inversion input terminal (−) of the IS comparator 44. The output signal of the slope compensation circuit 35 is supplied to the non-inversion input terminal (+) of the IS comparator 44. A power supply voltage Vcc is connected via a resistor R0 to the FB terminal, and the resistance R0 is the load resistance of a phototransistor configuring the photocoupler 21. Because of this, the size of the load 25 connected to the switching power supply device is detected from the drop in voltage from the power supply voltage Vcc according to the resistance R0.
The slope-compensated IS terminal voltage and the level-shifted FB terminal voltage are compared in the IS comparator 44, thus determining the timing at which the MOSFET 17 is turned off. Also, an OCP comparator 45 that determines the overcurrent protection level of the MOSFET 17 is connected to the IS terminal of the control IC 8. The non-inversion input terminal (+) of the OCP comparator 45 is connected to the IS terminal and the inversion input terminal (−) is connected to a reference power supply V3, respectively, and the OCP comparator 45 determines the overcurrent protection level of the MOSFET 17. Further, an off-state signal from the IS comparator 44 and an off-state signal from the OCP comparator 45 are both supplied via an OR gate 46 to the reset terminal of the RS flip-flop 38.
Current from a current source 47 is supplied via the LAT terminal to the thermistor 9. An LAT comparator 48 is connected to the LAT terminal and a reference power supply V4 and, on detecting that the voltage of the LAT terminal (that is, the voltage of the thermistor 9) has fallen to or below the voltage of the reference power supply V4, determines that there is a heated condition, and outputs a set signal to a latch circuit 49. The latch circuit 49 receives the set signal of the LAT comparator 48, and outputs an H level latch signal Latch to the OR gate 41 and an OR gate 51. Because of this, the drive circuit 42 and start-up circuit 31 are turned off. Also, the UVLO signal of the low voltage malfunction prevention circuit 32 is supplied to the reset terminal of the latch circuit 49, and a latching condition is deactivated when the potential of the VCC terminal falls.
On the internal power supply 33 starting up and power being supplied to the internal circuit, voltage is applied via the resistor R0 and FB terminal to the phototransistor configuring the photocoupler 21, and the FB terminal voltage rises. On the FB terminal voltage signal rising to or above a constant voltage value, the oscillating signal Dmax is output from the oscillator 34, and a set pulse is output from the one-shot circuit 37 to the RS flip-flop 38, triggered by the rise of the oscillating signal Dmax. The set pulse is input into the OR gate 39 together with the output signal of the RS flip-flop 38, and a blanking signal is generated as heretofore described. Further, this signal is output as a PWM signal from the OUT terminal, via the AND gate 40 and drive circuit 42, to the gate terminal of the MOSFET 17, becoming the switch signal Sout and driving the MOSFET 17. Because of this, the MOSFET 17 is turned on at the rise of the oscillating signal Dmax. Taking the sum (OR) of the output signal of the RS flip-flop 38 and the set pulse from the one-shot circuit 37 is done so that, even in a condition wherein the RS flip-flop 38 is left reset for some reason, the MOSFET 17 is turned on for the duration of the set pulse from the one-shot circuit 37. As the drain current Ids flows through the sense resistor 12 when the MOSFET 17 is turned on, the voltage of the IS terminal of the control IC 8 rises.
Further, on the slope-compensated IS terminal voltage of the control IC 8 reaching a voltage which is the FB terminal voltage level-shifted by the level shift circuit 43, a reset signal is output from the IS comparator 44 to the RS flip-flop 38 via the OR gate 46. By the RS flip-flop 38 being reset, the output of the OR gate 39 changes to an L level (during normal operation, the set pulse from the one-shot circuit 37 is at an L level at this point), and as the output of the AND gate 40 also changes to an L level in response, the MOSFET 17 is turned off by the switch signal Sout.
Also, even in the event that the load 25 connected to the switching power supply device becomes extremely heavy, and the voltage value fed back to the FB terminal of the control IC 8 is outside the (high voltage side) control range, it is possible, by comparing the voltage value of the IS terminal with the constant reference voltage value V3 using the OCP comparator 45, to turn off the MOSFET 17 when the voltage value of the IS terminal is equal to or higher than the reference voltage value V3.
Before the level-shifted FB terminal voltage is compared with the IS terminal voltage in the IS comparator 44, slope compensation whereby a slope compensation voltage proportional to the on-state duration of the MOSFET 17 is added is carried out on the IS terminal voltage by the slope compensation circuit 35. Generally, provided that the MOSFET 17 is operating in a steady state, the sizes of the current flowing through the MOSFET 17 at the start and end of the switching cycle coincide. However, when the duty cycle (on-state time ratio=on-state time duration/switching cycle) of the MOSFET 17 becomes too long, the sizes of the current are no longer able to coincide, and the condition of the current flowing through the MOSFET 17 fluctuates with each switching cycle. This kind of oscillation at low frequency is known as sub-harmonic oscillation, but there are conditions for this sub-harmonic oscillation to occur. Sub-harmonic oscillation can be prevented by slope compensation whereby a monotonically increasing signal is superimposed on the IS terminal voltage, thus preventing the conditions from being established (refer to PTL 1).
FIG. 7 is a circuit diagram showing one example of a heretofore known slope compensation circuit, while FIG. 8 is a timing diagram showing a slope compensation signal generated by the slope compensation circuit of FIG. 7.
Hereafter, a description will be given, based on the timing chart shown in FIG. 8, of a slope compensation operation in the slope compensation circuit 35.
In FIG. 7, the IS terminal voltage signal is input into an input terminal 35a, while the oscillating signal Dmax of the oscillator 34 is input into an input terminal 35b. The gate terminal of each of a serially-connected p-channel transistor M1 and n-channel transistor M2 is connected via an inverter 351 to the input terminal 35b. Of the serially-connected transistors M1 and M2, the source terminal of the M1 is connected to a current source circuit I1, the source terminal of the M2 is grounded, and the commonly connected drain terminals are connected to the base of a PNP transistor T1. Also, a connection point of the transistors M1 and M2 is connected to one end of a capacitor C1, while the other end of the capacitor C1 is grounded.
The emitter of the PNP transistor T1 is connected to the base of an NPN transistor T2 and a current source circuit I2, while the collector of the PNP transistor T1 is grounded. The collector of the NPN transistor T2 is connected to the power supply Vcc, while the emitter of the NPN transistor T2 is connected via serially-connected resistors R1 and R2 and the input terminal 35a to the IS terminal. Also, a connection point of the resistors R1 and R2 is connected to an output terminal 35c. 
The slope compensation circuit 35 with the heretofore described configuration is such that the oscillating signal Dmax from the oscillator 34 is supplied to the input terminal 35b, and when the oscillating signal Dmax is at an H level, the transistor M1 is turned on, the transistor M2 is turned off, and the capacitor C1 is charged by the current from the current source circuit I1. This monotonically increasing integrated voltage is applied to the base of the PNP transistor T1 as the kind of continuously rising voltage signal Sa shown in FIG. 8. The voltage signal Sa is level shifted by two emitter followers formed one by each of the PNP transistor T1 and NPN transistor T2 (the level shift amount=(the base-emitter voltage of the PNP transistor T1)−(the base-emitter voltage of the NPN transistor T2)≈0), and a voltage of the same level as the voltage signal Sa is generated at the emitter of the NPN transistor T2. Also, as shown by a dotted line in FIG. 8, the IS terminal voltage signal also rises continuously from a timing t1 at which the MOSFET 17 is turned on. The inclination of the voltage signal is determined by the inductance value of the primary winding 16 of the transformer T shown in FIG. 5 and the input voltage from the AC input 1 (the voltage value of the capacitor 5). It can be assumed that the voltage value of the capacitor 5 is constant within one switching cycle.
Herein, the rise of the oscillating signal Dmax and the turning on of the MOSFET 17 occur at the same timing, because of which, taking the resistance values of the resistors R1 and R2 to be R1 and R2 respectively, the waveform of the voltage signal Sa is added at a voltage division ratio (R1/(R1+R2)) to the IS terminal voltage signal, and output from the output terminal 35c. The voltage waveform of the output terminal 35c is compared in the IS comparator 44 with the feedback voltage waveform from the FB terminal shown in FIG. 6 level shifted by the level shift circuit 43, and when the voltage of the output terminal 35c rises above the level-shifted feedback voltage, the output of the IS comparator 44 changes to an H level. This signal resets the RS flip-flop 38 via the OR gate 46, and as an output Q of the RS flip-flop changes to an L level, the MOSFET 17 is turned off by the drive circuit 42.
At a timing t2 at which the oscillating signal Dmax changes to an L level, the transistor M2 is turned on, and the charge of the capacitor C1 is swiftly released. Because of this, the output voltage of the slope compensation circuit 35 (the voltage of the output terminal 35c) becomes zero, voltage is added again from zero potential when the MOSFET 17 is next turned on, and the switching power supply device is subject to the PWM controlling.
FIG. 9 is a circuit diagram showing one example of a heretofore known oscillator including a frequency modulating function.
The heretofore known oscillator 34 shown in FIG. 9 is configured of current source circuits I3 and I4, which cause a constant current to flow, a p-channel transistor M3 connected via the current source circuit I3 to the power supply Vcc, an n-channel transistor M4 connected in series to the transistor M3 and grounded via the current source circuit I4, a timing capacitor C2, one end of which is connected to a connection point of the transistors M3 and M4 and the other end of which is grounded, comparators 341 and 342 that set a charge voltage upper limit value and discharge voltage lower limit value respectively of a voltage signal Sb of the timing capacitor C2, a frequency modulating modulation period setting circuit 343, to be described hereafter, an AND gate 344 into which an output signal Sc of the modulation period setting circuit 343 and the output signal of the comparator 341 are input, an RS flip-flop 345 that turns the transistors M3 and M4 on and off in a complementary way, and an inverter 346. When it is determined from the feedback signal to the FB terminal that there is a light load condition, the oscillator 34 functions so as to reduce the switching frequency by reducing the current values of the current source circuits I3 and I4, but with regard to the description of the oscillator, it may be supposed that the current is constant.
A first reference voltage V5 is input into the inversion input terminal (−) of the comparator 341, while a second reference voltage V6 is input into the non-inversion input terminal (+) of the comparator 342. The first reference voltage V5 and second reference voltage V6 specify the charge voltage upper limit value and discharge voltage lower limit value respectively of the voltage signal Sb of the timing capacitor C2, and have a relationship such that V5>V6. The output terminal of the comparator 342 is connected to a set terminal S of the RS flip-flop 345, while the output terminal of the comparator 341 is connected via the AND gate 344 to a reset terminal R of the RS flip-flop 345. The Q output (the signal output from the output terminal Q is taken to be the Q output) of the RS flip-flop 345 is supplied from the RS flip-flop 345 to an output terminal 34a of the oscillator 34, output as the oscillating signal Dmax, and connected via the inverter 346 to the gate of each of the transistors M3 and M4.
Now, it will be assumed that the output terminal of the comparator 341 is connected directly to the reset terminal R of the RS flip-flop 345, and that the oscillator 34 has no frequency modulating modulation period setting function. In this case, on the voltage signal Sb of the timing capacitor C2 reaching the first reference voltage V5 input into the inversion input terminal of the comparator 341 at the timing at which the timing capacitor C2 is charged by the current from the current source circuit I3, the flip-flop 345 is immediately reset, and the on and off-states of the transistors M3 and M4 are inverted. Because of this, the timing capacitor C2 is discharged by the current of the current source circuit I4, and on the voltage signal Sb reaching the second reference voltage V6 input into the non-inversion input terminal of the comparator 342, the flip-flop 345 is immediately set, and the on and off-states of the transistors M3 and M4 are inverted again. In this way, an operation whereby the timing capacitor C2 is charged by the current source circuit I3 then discharged by the current source circuit I4 is repeated. Consequently, the length of timings t1 to t4 shown in FIG. 10, to be described hereafter, is specified by the total duration of the charging period and discharging period of the timing capacitor C2 (the length of t2 to t3 is zero). Because of this, the switching frequency of the MOSFET 17 shown in FIG. 5 is determined by the timing capacitor C2 alone, while the maximum duty cycle is specified by only the charging period and discharging period of the timing capacitor C2.
As opposed to this, the oscillator 34 of FIG. 9 equipped with the frequency modulating function is such that it is possible, using the modulation period setting circuit 343, to provide a modulation period (idle period), whose temporal length fluctuates with each cycle, between the charging period and discharging period. Consequently, the cycle of the oscillator 34 oscillating signal, that is, the switching cycle of the switching power supply, is the sum of the charging period, the modulation period (idle period), and the discharging period.
The modulation period setting circuit 343 is configured of an inverter 347 that inverts the output signal of the comparator 341, a current source circuit I5 connected to the power supply Vcc, a p-channel transistor M5 and n-channel transistor M6, whose gate terminals are connected to the output terminal of the inverter 347 and which are turned on and off alternately, a counter 348 that sets an idle period, p-channel transistors M71, M72 to M7n selected by an n-bit on/off signal of the counter 348, and capacitors C31, C32 to C3n connected in series to the transistors M71, M72 to M7n respectively.
FIG. 10 is a timing diagram showing a signal waveform of each portion of the oscillator.
Herein, a description will be given of the waveform of the oscillating signal Dmax shown in FIG. 10 output from the oscillator 34.
The oscillator 34 shown in FIG. 9 is such that, although the operation of charging the timing capacitor C2 finishes at the timing t2, a modulation period (idle period t2 to t3) is provided from the timing t2 to t3, rather than starting discharging immediately after the charging operation. That is, the modulation period setting circuit 343 is such that when the operation of charging the timing capacitor C2 finishes, the current of the current source circuit I5 starts charging the capacitors C31, C32 to C3n via the selected transistors M71, M72 to M7n. The operation of discharging the timing capacitor C2 starts at a timing t3 at which the charging of the capacitors C31, C32 to C3n is completed (that is, the timing at which the voltage Sc, which is the charge voltage of the capacitors C31, C32 to C3n, reaches a threshold value voltage with respect to the input of the AND gate 344). The modulation period setting circuit 343 is such that the capacitance values of the capacitors C31, C32 to C3n can be switched by turning on or off the switches of the p-channel transistors M71, M72 to M7n, because of which the length of the charging period of the capacitors C31, C32 to C3n, that is, the modulation period (idle period t2 to t3), varies. In this way, the oscillator 34 is such that it is possible, using the modulation period setting circuit 343, to set a modulation period (idle period t2 to t3) between the frequency fixing periods (t1 to t2, t3 to t4) of the oscillating signal Dmax of the oscillator 34.
In this way, the modulating method of the oscillator 34 equipped with a frequency modulating function is such that it is possible to modulate the frequency of the oscillating signal Dmax by modulating the idle period t2 to t3 of the timing capacitor C2. This is because the switching cycle of the MOSFET 17 is specified by the total of the charging period (t1 to t2) of the timing capacitor C2, the charging period (t2 to t3) of the capacitors C31, C32 to C3n, and the discharging period (t3 to t4) of the timing capacitor C2. In this way, it is possible to modulate the switching frequency of the switch signal Sout by modulating the idle period of the timing capacitor C2. Further, the charging period of the capacitors C31, C32 to C3n is inversely proportional to the total capacitance value of the capacitors connected to the current source circuit I5, and which capacitors are to be connected is determined by the p-channel transistors M71, M72 to M7n, which are turned on or off in accordance with the count value of the counter 348, which value is lowered or raised with each cycle of the oscillating signal Dmax (each switching cycle) (refer to PTL 2).
Regarding the way of modulating the switching cycle, various methods have been proposed to date, apart from that heretofore described.
The control IC 8 described above is such that level limitation is carried out by the OCP comparator 45 so that the drain current Ids flowing through the MOSFET 17 does not rise to or above the constant current. This is as has already been described based on FIG. 6, which shows the internal circuit configuration of the IC 8.
FIGS. 11A and 11B are diagrams showing changes in the overcurrent protection level when the input voltage changes.
The MOSFET 17 is turned off after the size of the drain current Ids flowing when the MOSFET 17 is in an on-state reaches an overcurrent detection level, but a certain delay time r is needed until the drain current Ids is actually cut off, as shown in FIG. 11A. The length of the delay time τ is specified by a current detecting terminal noise filter, circuit delay factors inside the control IC 8, a delay time in the switching operation of the MOSFET 17 itself, or the like. Further, when the input voltage from the AC input 1 is high, the inclination of the current flowing through the primary winding 16 of the transformer T when the MOSFET 17 is turned on increases, as shown in FIG. 11B. Although the angle of inclination also depends on the inductance value of the primary winding 16, the inclination when the input voltage is low is gentle, as shown in FIG. 11A, while the inclination is steep when the input voltage is high.
However, as shown in FIG. 6, the overcurrent detection voltage in the OCP comparator 45 is set to a constant value in accordance with the reference power supply V3. Because of this, the inductance current (=Ids) flowing during the delay time r continues to rise, and the current limit value when the MOSFET 17 is actually turned off is such that the higher the input voltage from the AC input 1, the higher the value of the peak current when an overcurrent protection operation is carried out. Generally, as the current limit value set for the load 25 is determined in accordance with the overcurrent detection level when the input voltage is low, a current higher than the overcurrent detection level desired by the designer flows when the input voltage is high. Consequently, the heretofore known flyback power supply whose PWM is to be controlled is such that it is necessary to increase the rated current of the MOSFET 17, transformer T, and the like, which is a factor leading to an increase in the cost and size of the power supply device.